Sample-and-hold circuits are used to sample an input voltage at a particular instant of time and hold the instantaneous value of the input voltage for a predetermined period of time. In a simple sample-and-hold circuit a capacitor is utilized to hold the sampled input voltage. An electronic switch provides a means for rapidly charging the capacitor to the sample voltage and then removing the input so that the capacitor can retain the sampled voltage. This stored voltage signal may thereafter be used as an input to other circuits.
While MOS devices are well suited for use as electronic switches, in practice they are not perfect and various departures from the ideal occur. A well-known charge injection problem exists whenever MOS devices are used as switches due to the parasitic capacitance between the source-drain and gate of a MOS switch. Also, during the sample period the MOS switch stores charge in the channel, part of which is injected into the storage capacitor when the switch opens, altering the voltage stored on the capacitor.
The charge injection error introduced by the switch is directly proportional to the size of the MOS switch, therefore voltage offset could be controlled by limiting the size of the switch. However, to permit fast and complete charging of the storage capacitor it is desirable to have a switch with low on-resistance. This requirement for low on-resistance results in the use of a switch which is relatively large compared to the size desired to keep charge injection error at a minimum.
One way of decreasing switch-induced voltage offset in sample-and-hold circuits is shown in U.S. Pat. No. 4,308,468 issued Dec. 29, 1981, to Gaylord G. Olson. The sample-and-hold circuit disclosed therein includes a first MOSFET switch for charging a storage capacitor and second compensating MOSFET switch connected to the node between the capacitor and the first switch. However, this second compensating MOSFET switch is biased so that it never turns on. The control signal provided to the second MOSFET switch is identical in timing but opposite in polarity to the control signal provided to the first switch so that the second switch stores a charge which will offset the switch-induced charge injection error caused by the first switch.
The solution for switch-induced error presented above may reduce charge injection errors but it does not deal with the effects of variations in charge injection characteristics from one switching device to another. Charge injection errors are reduced only so far as the charge injection characteristics of the two switches are identical. The quantity of charge not canceled remains proportional to the size of the switches used.
Other solutions have been proposed for reducing charge injection errors, such as those disclosed in U.S. Pat. Nos. 4,467,227; 4,570,080 and 4,585,956. However, these references present more complicated circuit constructions requiring three or more switches, correction capacitors, feedback circuits, or the use of several timing signals to control switch operations.